It is desirable in, for example, wearable or Internet of Things (IoT) devices, to minimize battery power drain to prolong operational life. Such devices typically have a number of operational modes including a state sometimes referred to as retention power saving where the supply voltage is reduced to a level compatible with retaining information, but too low for any functional activity. The purpose of the reduction in supply voltage is to reduce the both the active and leakage power associated with any circuit blocks associated with the supply. The device may spend a significant percentage of time in this mode hence it is desirable to minimize power drain and hence increase operational life. It is a common feature of such devices where the power supply is periodically brought out of retention for a short period of activity, for example to respond to an interrupt, or to receive a signal from a second device.
The supply voltage will typically have a large associated bulk capacitor to provide supply decoupling. The combination of this bulk capacitor and the repetitive transitioning in and out of retention state results in ‘lost’ power associated with charge and discharge of the bulk capacitor. Effects of bulk capacitor charging has not previously been considered or regarded as problematic since in previous applications the supply voltage can be considered as effectively stable and any current associated with the bulk capacitor charging is insignificant compared to the load current. For example DVFS (voltage and frequency scaling) may be applied to reduce supply voltage in response to activity in normal operation mode where the active current is far greater than the bulk cap charge current. The net consequence of this effect is to undesirably shorten the battery life and/or periods between recharging.
For example, in some process nodes the normal operation voltage may be 1.8V and the retention voltage may be 1.2V and in some wearable devices the supply may transition between these two voltage nodes between 10 to 100 times a second and the bulk capacitance may be 10 uF. The power associated with transitioning the voltage on the bulk capacitor is analogous to the power in CMOS circuits associated with clocking the CMOS gates which can be calculated from the well-known formula:Power=Cgate×Vcc^2×freq=Vcc×Icharge.Substituting above conditions:I charge=10 uF×(1.8−1.2)×10=60 uA
Therefore the average current drain associated with transitioning the bulk capacitor 10 times a second is 60 uA, which is unacceptable in the context of retention current being typically <1 uA
In addition, in application the supply rail has to be dynamically switched by, for example, a switched mode regulator between the two voltage states to benefit from the lower current in retention voltage since the retention current is insufficient to discharge the bulk cap in an acceptable time to deliver any power saving benefits. For example consider the above example in 10 msec a current of 1 uA will only discharge a 10 uF capacitor by 1 mV therefore without active switching the device will never enter retention voltage state. It will actually take 6 seconds to fully transition by discharge alone (assuming a constant load of 1 uA).
It may be therefore argued that retention power saving can never be realistically implemented in applications where the device exits retention setting at a low Hz repetition rate unless the voltage source contains a means to actively transition between the voltage levels, which will consume power.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.